/*---------- Registers for M1 ----------*/
register M1_srcip
{
    width: 32;
    instance_count: M1_SIZE;
}
register M1_dstip
{
    width: 32;
    instance_count: M1_SIZE;
}
register M1_proto
{
    width: 8;
    instance_count: M1_SIZE;
}
register M1_cnt
{
    width: 32;
    instance_count: M1_SIZE;
}

/*---------- Registers for M2 ----------*/
register M2_srcip
{
    width: 32;
    instance_count: M2_SIZE;
}
register M2_dstip
{
    width: 32;
    instance_count: M2_SIZE;
}
register M2_proto
{
    width: 8;
    instance_count: M2_SIZE;
}
register M2_cnt
{
    width: 32;
    instance_count: M2_SIZE;
}

/*---------- Registers for M3 ----------*/
register M3_srcip
{
    width: 32;
    instance_count: M3_SIZE;
}
register M3_dstip
{
    width: 32;
    instance_count: M3_SIZE;
}
register M3_proto
{
    width: 8;
    instance_count: M3_SIZE;
}
register M3_cnt
{
    width: 32;
    instance_count: M3_SIZE;
}

/*---------- Registers for A ----------*/
register A
{
 width: 16; // register_lo is for the digest field, and register_hi is for the count field 
 instance_count: A_SIZE;
}

/*---------- Register for Resubmission ----------*/
register resubmission_counter {
 width: 64;
 instance_count: 1;
}
/*----------*/

/*++++++++++ Register for Packet Count ++++++++++*/
register counter1 { // for m_meta.M1_cnt
 width: 32;
 instance_count: 1;
}

register counter2 { // for m_meta.M2_cnt
 width: 32;
 instance_count: 1;
}

register counter3 { // for m_meta.M3_cnt
 width: 32;
 instance_count: 1;
}

register counter4 { // for m_meta.A_cnt
 width: 8;
 instance_count: 1;
}

register counter5 { // for m_meta.flag
 width: 32;
 instance_count: 1;
}
/*----------*/

